1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a technology for generating a programming current pulse.
2. Related Art
A phase change random access memory (PCRAM) is a non-volatile memory apparatus which programs a memory cell through a programming current pulse.
A PCRAM has a characteristic of a non-volatile memory and can achieve a random access. Also, the PCRAM can be highly integrated at a low cost. The PCRAM stores data by using a phase change material. Specifically, the PCRAM stores data by using a phase change of a phase change material according to a temperature condition, that is, a change in a resistance value according to a phase change.
A phase change material can change to an amorphous state or a crystalline state according to a temperature condition. A representative phase change material is a chalcogenide alloy. A representative chalcogenide alloy is Ge2Sb2Te5 composed of germanium (Ge), antimony (Sb), and tellurium (Te). Hence, a phase change material is generally called a “GST”.
A PCRAM uses Joule heating generated when a current or voltage is applied to the phase change material (GST) to cause a reversible phase change of a phase change material (GST) between a crystalline state and an amorphous state. In circuit terms, the crystalline state is referred to as a set state. In the set state, the phase change material (GST) has electrical properties substantially equal to those of a metal having a small resistance value. In circuit terms, the amorphous state is referred to as a reset state. In the reset state, the phase change material (GST) has a larger resistance value than that in the set state. That is to say, the PCRAM stores data through a change in a resistance value between the crystalline state and the amorphous state, and determines a level of the stored data by sensing a current flowing through the phase change material (GST) or a voltage change depending on a current change. Generally, the set state is defined as a logic level of ‘0’, and the reset state is defined as a logic level of ‘1’. A state of the phase change material (GST) is continuously maintained even though power is interrupted.
The amorphous state and the crystalline state of the phase change material (GST) may also be changed by a programming current pulse. A set programming current pulse is a programming current which changes the phase change material (GST) of a memory cell to the set state, and a reset programming current pulse is a programming current which changes the phase change material (GST) of the memory cell to the reset state.
The phage change material (GST) is changed to an amorphous state when the GST is heated to a temperature higher than a melting temperature for a predetermined time and then rapidly cooled. A phage change material (GST) is changed to a crystalline state when the GST is heated to a temperature that is higher than a crystallization temperature and lower that the melting temperature for a preselected time.
Because a resistance value can vary depending upon an amorphous volume or a crystalline volume of the phase change material (GST), a memory cell can be configured in a multi-level form. In general, a large current is flowed as the reset programming current pulse for a time shorter than the set programming current pulse, and a small current is flowed as the set programming current pulse for a time longer than the reset programming current pulse.
FIG. 1 is a diagram illustrating a memory cell of a conventional PCRAM.
Referring to FIG. 1, a memory cell includes a cell diode D1 and a phase change element GST.
The basic operations of the PCRAM configured as mentioned above will be described below.
First, an operation for programming data to the phase change element GST is performed as follows: when a word line WL is activated to a low level, i.e., a ground voltage, and a specified voltage begins to be applied through a bit line BL, since a cell diode D1 becomes a forward biased state, the cell diode D1 is turned on. A current path is formed among the bit line BL, the phase change element GST, and the word line WL. Therefore, a current pulse corresponding to data is supplied to the phase change element GST through the bit line BL, which changes the phase change element GST to the crystalline state or the amorphous state. In general, if data to be programmed has a logic level of ‘1’, the phase change element GST is changed to a reset state by supplying a reset programming current pulse. If data to be programmed has a logic level of ‘0’, the phase change element GST is changed to a set state by supplying a set programming current pulse. The reset state as the amorphous state has a larger resistance value than the set state as the crystalline state.
Also, an operation for detecting data programmed to the phase change element GST is performed as follows:
when the word line WL is activated to the low level, i.e., the ground voltage, and the specified voltage begins to be applied through the bit line BL, since the cell diode D1 becomes the forward biased state, the cell diode D1 is turned on from when the voltage difference between the anode and the cathode of the cell diode D1 is higher than the threshold voltage. The current path is formed among the bit line BL, the phase change element GST, and the word line WL. Therefore, when a specified voltage or a specified current is applied to the phase change element GST through the bit line BL, an amount of current flowing through the phase change element GST or the magnitude of a voltage drop in the phase change element GST varies depending upon the resistance value of the phase change element GST. Therefore, by using this fact, data stored in the phase change element GST is discriminated. That is to say, a state of the phase change element GST is discriminated.
FIG. 2 is a configuration diagram of a data write unit of the conventional PCRAM.
Referring to FIG. 2, a data write unit includes a current control section 10, a current driving section 20, and a selection section 30.
The current control section 10 is configured to control a voltage level of a control node N1 in response to a set control signal SETP and a reset control signal RESETP when a write enable signal WDEN is activated. Current driving forces of an NMOS transistor MN1 controlled by the set control signal SETP and an NMOS transistor MN2 controlled by the reset control signal RESETP are designed to be different from each other. The set control signal SETP and the reset control signal RESETP are inputted in a pulse type.
The current driving section 20 is configured to drive a programming current pulse I_PGM with a magnitude corresponding to the voltage level of the node N1, to an output terminal N2. The programming current pulse I_PGM can be classified into a set programming current pulse corresponding to the set control signal SETP and a reset programming current pulse corresponding to the reset control signal RESETP.
The selection section 30 is configured to output the programming current pulse I_PGM driven from the current driving section 20 to bit lines BL0 through BL3 which respectively correspond to a plurality of select signals YSW<0:3>.
FIG. 3 is a graph showing programming current pulses which are outputted from the data write unit of FIG. 2.
Referring to FIG. 3, it is to be appreciated that a reset programming current pulse may be driven for a short time to a temperature higher than a melting temperature of GST. On the other hand, a set programming current pulse may be driven for a longer time when compared to the reset programming current pulse, and the reset programming pulse may be driven to a temperature below the melting temperature of GST but above the crystallization temperature of GST. For reference, in FIG. 3, the reset programming current pulse is shown as an amorphizing pulse, and the set programming pulse is shown as a crystallizing pulse. In general, the greater the magnitude of the reset programming current pulse, the greater the resistance value of a phase change memory cell increases. Also, the longer the supply time of the set programming current pulse, the longer the phase change memory cell retains its resistance value.
Meanwhile, in a semiconductor memory apparatus, a number of phase change memory cells are provided, and the programming characteristics of the respective phase change memory cells are different due to variables in processes. That is to say, even though a programming current pulse of the same magnitude is applied for the same time, the phase change memory cells are programmed with different resistance values due to different programming characteristics. In other words, consistency and stability in resistance values is lacking when programming a plurality of phase change memory cells with different programming characteristics.